I2S_CER

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Interpret as I2S_CER

CLKEN=Val_0x0

Description

Clock Enable Register

Fields

CLKEN

Clock Generation Enable or Disable. This bit enables or disables the clock generation signals when the I2S module is a master: SCLK_EN, WS_OUT, and SCLK_GATE. For more information about clock generation, refer to Section I2S Clocks.

0 (Val_0x0): Clock generation disabled

1 (Val_0x1): Clock generation enabled

Links

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